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| AM29LV033C 32 Megabit (4 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES SOFTWARE FEATURES s Zero Power Operation -- Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero s Supports Common Flash Memory Interface (CFI) s Erase Suspend/Erase Resume -- Suspends erase operations to allow programming in same bank s Package options -- 63-ball FBGA -- 40-pin TSOP s Data# Polling and Toggle Bits -- Provides a software method of detecting the status of program or erase cycles s Compatible with JEDEC standards -- Pinout and software compatible with single-power-supply flash standard s Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES s Single power supply operation -- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications -- Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors s Any combination of sectors can be erased s Ready/Busy# output (RY/BY#) -- Hardware method for detecting program or erase cycle completion s Flexible sector architecture -- Sixty-four 64 Kbyte sectors s Hardware reset pin (RESET#) -- Hardware method of resetting the internal state machine to the read mode s Manufactured on 0.32 m process technology PERFORMANCE CHARACTERISTICS s ACC input pin -- Acceleration (ACC) function provides accelerated program times s High performance -- Access times as fast as 70 ns -- Program time: 7 s/byte typical utilizing Accelerate function s Sector protection -- Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector -- Temporary Sector Unprotect allows changing data in protected sectors in-system s Ultra low power consumption (typical values) -- 2 mA active read current at 1 MHz -- 10 mA active read current at 5 MHz -- 200 nA in standby or automatic sleep mode s Minimum 1 million write cycles guaranteed per sector s 20-year data retention at 125C -- Reliable operation for the life of the system s Command sequence optimized for mass storage -- Specific addresses not required for unlock cycles This Data Sheet states AMD's current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 22268 Rev: B Amendment/+2 Issue Date: Novembe 7, 2000 GENERAL DESCRIPTION The AM29LV033C is a 32 Mbit, 3.0 Volt-only Flash memory organized as 4,194,304 bytes. The device is offered in 63-ball FBGA and 40-pin TSOP packages. The byte-wide (x8) data appears on DQ7-DQ0. All read, program, and erase operations are accomplished using only a single power supply. The device can also be programmed in standard EPROM programmers. The standard device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection. 2 AM29LV033C TABLE OF CONTENTS Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . 2 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Standard Products .................................................. 8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9 Table 1. AM29LV033C Device Bus Operations ............9 Figure 5. Data# Polling Algorithm................................ 24 RY/BY#: Ready/Busy# ......................................... 25 DQ6: Toggle Bit I .................................................. 25 DQ2: Toggle Bit II ................................................. 25 Reading Toggle Bits DQ6/DQ2 ............................ 25 DQ5: Exceeded Timing Limits .............................. 26 DQ3: Sector Erase Timer ..................................... 26 Figure 6. Toggle Bit Algorithm..................................... 26 Table 10. Write Operation Status ................................27 Requirements for Reading Array Data ................... 9 Writing Commands/Command Sequences ............ 9 Accelerated Program Operation ........................... 10 Program and Erase Operation Status .................. 10 Standby Mode ...................................................... 10 Automatic Sleep Mode ......................................... 10 RESET#: Hardware Reset Pin ............................. 10 Output Disable Mode ............................................ 11 Table 2. AM29LV033C Sector Address Table ............11 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 28 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 28 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29 CMOS Compatible ............................................... 29 Zero Power Flash ................................................. 30 Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ................................... 30 Figure 10. Typical ICC1 vs. Frequency ......................... 30 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 11. Test Setup.................................................. 31 Table 11. Test Specifications ......................................31 Autoselect Mode ................................................... 13 Table 3. AM29LV033C Autoselect Codes (High Voltage Method) ................................................13 Key to Switching Waveforms . . . . . . . . . . . . . . . 31 Figure 12. Input Waveforms and Measurement Levels ................................................... 31 Sector/Sector Block Protection and Unprotection 13 Table 4. Sector Block Addresses for Protection/Unprotection ...............................................14 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32 Read Operations .................................................. 32 Figure 13. Read Operations Timings .......................... 32 Temporary Sector/Sector Block Unprotect ........... 14 Figure 1. Temporary Sector Unprotect Operation....... 14 Figure 2. In-System Sector Protect/ Unprotect Algorithms................................................... 15 Hardware Reset (RESET#) .................................. 33 Figure 14. RESET# Timings........................................ 33 Erase/Program Operations ................................... 34 Figure 15. Program Operation Timings ....................... 35 Figure 16. Accelerated Program Timing Diagram ....... 35 Figure 17. Chip/Sector Erase Operation Timings........ 36 Figure 18. Data# Polling Timings (During Embedded Algorithms)................................................ 37 Figure 19. Toggle Bit Timings (During Embedded Algorithms)................................................ 37 Figure 20. DQ2 vs. DQ6.............................................. 37 Figure 21. Temporary Sector/Sector Block Unprotect Timing Diagram................................. 38 Figure 22. Sector Protect/Unprotect Timing Diagram ........................................................... 39 Figure 23. Alternate CE# Controlled Write Operation Timings ....................................................... 41 Hardware Data Protection .................................... 16 Low VCC Write Inhibit ............................................ 16 Write Pulse "Glitch" Protection ............................. 16 Logical Inhibit ....................................................... 16 Power-Up Write Inhibit ......................................... 16 Common Flash Memory Interface (CFI) . . . . . . . 16 Table 5. CFI Query Identification String ......................16 Table 6. System Interface String .................................17 Table 7. Device Geometry Definition ..........................17 Table 8. Primary Vendor-Specific Extended Query ....18 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 19 Reading Array Data .............................................. 19 Reset Command .................................................. 19 Autoselect Command Sequence .......................... 19 Byte Program Command Sequence ..................... 19 Unlock Bypass Command Sequence ................... 20 Accelerated Program Operations ......................... 20 Figure 3. Program Operation ...................................... 20 Chip Erase Command Sequence ......................... 20 Sector Erase Command Sequence ...................... 21 Erase Suspend/Erase Resume Commands ......... 21 Figure 4. Erase Operation........................................... 22 Table 9. AM29LV033C Command Definitions ...........23 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 24 DQ7: Data# Polling ............................................... 24 Erase and Programming Performance . . . . . . . 42 Latchup Characteristics . . . . . . . . . . . . . . . . . . . 42 TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 42 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 43 TS 040--40-Pin Standard TSOP ......................... 43 TSR040--40-Pin Reverse TSOP ........................ 44 FBD063--63-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm ............................................... 45 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46 Revision B (January 3, 2000) ............................... 46 Revision B+1 (February 21, 2000) ....................... 46 Revision B+2 (November 7, 2000) ....................... 46 AM29LV033C 3 PRODUCT SELECTOR GUIDE Family Part Number Speed Option Max Access Time (ns) CE# Access (ns) OE# Access (ns) Full Voltage Range: VCC = 2.7-3.6 V -70 70 70 30 AM29LV033C -90 90 90 40 -120 120 120 50 Note: See "AC Characteristics" for full specifications. BLOCK DIAGRAM RY/BY# VCC VSS RESET# Erase Voltage Generator Input/Output Buffers Sector Switches DQ0-DQ7 WE# ACC State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch CE# OE# STB VCC Detector Timer Address Latch Y-Decoder Y-Gating X-Decoder Cell Matrix A0-A21 4 AM29LV033C CONNECTION DIAGRAMS A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# ACC RY/BY# A18 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 VSS A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VCC VCC A21 DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0 40-Pin Standard TSOP A17 VSS A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VCC VCC A21 DQ3 DQ2 DQ1 DQ0 OE# VSS CE# A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40-Pin Reverse TSOP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A16 A15 A14 A13 A12 A11 A9 A8 WE# RESET# ACC RY/BY# A18 A7 A6 A5 A4 A3 A2 A1 AM29LV033C 5 CONNECTION DIAGRAMS 63-Ball FBGA (Top View, Balls Down) A8 NC* A7 NC* B8 NC* B7 NC* C7 A14 C6 A9 C5 WE# C4 RY/BY# C3 A7 D7 A13 D6 A8 D5 RESET# D4 ACC D3 A18 D2 A4 E7 A15 E6 A11 E5 NC E4 NC E3 A6 E2 A2 F7 A16 F6 A12 F5 NC F4 NC F3 A5 F2 A1 G7 A17 G6 A19 G5 DQ5 G4 DQ2 G3 DQ0 G2 A0 H7 NC H6 A10 H5 NC H4 DQ3 H3 NC H2 CE# J7 A20 J6 DQ6 J5 VCC J4 VCC J3 NC J2 OE# K7 VSS K6 DQ7 K5 DQ4 K4 A21 K3 DQ1 K2 VSS L8 NC* L7 NC* M8 NC* M7 NC* A2 NC* A1 NC* B1 NC* C2 A3 L2 NC* L1 M2 NC* M1 NC* * Balls are shorted together via the substrate but not connected to the die. NC* Special Handling Instructions for FBGA Packages Special handling is required for Flash Memor y products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. 6 AM29LV033C PIN CONFIGURATION A0-A21 = 22 addresses 8 data inputs/outputs Chip enable Output enable Write enable Hardware reset pin, active low Ready/Busy output Hardware Acceleration Pin 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) Device ground Pin not connected internally DQ0-DQ7 = CE# OE# WE# RESET# RY/BY# ACC VCC = = = = = = = LOGIC SYMBOL 22 A0-A21 DQ0-DQ7 8 CE# OE# WE# RESET# ACC RY/BY# VSS NC = = AM29LV033C 7 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. AM29LV033C -70 E C TEMPERATURE RANGE I = Industrial (-40C to +85C) E = Extended (-55C to +125C) PACKAGE TYPE E = 40-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 040) F = 40-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR040) WD = 63-ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 8 x 14 mm package (FBD063) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION AM29LV033C 32 Megabit (4 M x 8-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program and Erase Valid Combinations for TSOP Packages AM29LV033C-70 AM29LV033C-90 AM29LV033C-120 EI, FI EI, EE, FI, FE Valid Combinations for FBGA Packages Order Number AM29LV033C-70 AM29LV033C-90 AM29LV033C-120 WDI WDI, WDE Package Marking L033C70V L033C90V I, E L033C12V I Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 8 AM29LV033C DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of Table 1. Operation Read Write (Note 1) Standby Output Disable Reset Sector/Sector Block Protect (Note 2) Sector/Sector Block Unprotect (Note 2) Temporary Sector/Sector Block Unprotect the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. AM29LV033C Device Bus Operations OE# L H X H X H H X WE# H L X H X L L X RESET# H H VCC 0.3 V H L VID VID VID Addresses AIN AIN X X X Sector Addresses, A6 = L, A1 = H, A0 = L Sector Addresses A6 = H, A1 = H, A0 = L AIN DQ0-DQ7 DOUT DIN High-Z High-Z High-Z DIN, DOUT DIN, DOUT DIN CE# L L VCC 0.3 V L X L L X Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Don't Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. When the ACC pin is at VHH, the device enters the accelerated program mode. See "Accelerated Program Operations" for more information. 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector/Sector Block Protection and Unprotection" section. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifica- tions and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a byte, instead of four. The "Byte Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address AM29LV033C 9 space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Command Definitions" section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the ACC pin returns the device to normal operation. Note that the ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RESET# pin is driven low. Refer to the next section, "RESET#: Hardware Reset Pin". If the device is deselected during erasure or programming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The autom atic sle ep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table r e pr es en ts the a u tom a ti c s le ep m od e cu rr en t specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7-DQ0. Standard read cycle timings and ICC read specifications apply. Refer to "Write Operation Status" for more information, and to "AC Characteristics" for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device will be in the standby mode, but 10 AM29LV033C within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Table 2. Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AM29LV033C Sector Address Table A18 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address Range (in hexadecimal) 000000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1FFFFF A19 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 AM29LV033C 11 Table 2. Sector SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 A21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AM29LV033C Sector Address Table (Continued) A19 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A18 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address Range (in hexadecimal) 200000-20FFFF 210000-21FFFF 220000-22FFFF 230000-23FFFF 240000-24FFFF 250000-25FFFF 260000-26FFFF 270000-27FFFF 280000-28FFFF 290000-29FFFF 2A0000-2AFFFF 2B0000-2BFFFF 2C0000-2CFFFF 2D0000-2DFFFF 2E0000-2EFFFF 2F0000-2FFFFF 300000-30FFFF 310000-31FFFF 320000-32FFFF 330000-33FFFF 340000-34FFFF 350000-35FFFF 360000-36FFFF 370000-37FFFF 380000-38FFFF 390000-39FFFF 3A0000-3AFFFF 3B0000-3BFFFF 3C0000-3CFFFF 3D0000-3DFFFF 3E0000-3EFFFF 3F0000-3FFFFF Note: All sectors are 64 Kbytes in size. 12 AM29LV033C Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its c orresponding programm ing algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 3. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table ). Table 3 shows Table 3. the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 9. This method does not require VID. See "Writing specific address and data commands or sequences into the command register initiates device operations. Table 9 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data." for details on using the autoselect mode. AM29LV033C Autoselect Codes (High Voltage Method) A21 to A16 X X A15 to A10 X X A8 to A7 X X A5 to A2 X X DQ7 to DQ0 01h A3h 01h (protected) Description Manufacturer ID: AMD Device ID: AM29LV033C CE# L L OE# L L WE# H H A9 VID VID A6 L L A1 L L A0 L H Sector Protection Verification L L H SA X VID X L X H L 00h (unprotected) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care. Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term "sector" applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 4). The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented via two methods. The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 22 shows the timing diagram. This method uses standard microprocessor bus cycle tim- ing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only AMD flash devices. Publication number 22269 contains further details; contact an AMD representative to request a copy. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details. AM29LV033C 13 Table 4. Sector Block Addresses for Protection/Unprotection Sector/ Sector Block SA0 SA1-SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA62 SA63 A21-A16 000000 000001,000010, 000011 000100, 000101, 000110, 000111 001000, 001001, 001010, 001011 001100, 001101, 001110, 001111 010000, 010001, 010010, 010011 010100, 010101, 010110, 010111 011000, 011001, 011010, 011011 011100, 011101, 011110, 011111 100000, 100001, 100010, 100011 100100, 100101, 100110, 100111 101000, 101001, 101010, 101011 101100, 101101, 101110, 101111 110000, 110001, 110010, 110011 110100, 110101, 110110, 110111 111000, 111001, 111010, 111011 111100, 111101, 111110 111111 Sector/ Sector Block Size 64 Kbytes 192 (3x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 192 (4x64) Kbytes 64 Kbytes Temporary Sector/Sector Block Unprotect (Note: For the following discussion, the term "sector" applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 4). This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 21 shows the timing diagrams, for this feature. START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation 14 AM29LV033C START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT = 1 RESET# = VID Wait 1 s Temporary Sector Unprotect Mode No First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Wait 150 s Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 No No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Temporary Sector Unprotect Mode Increment PLSCNT Reset PLSCNT = 1 Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 No No PLSCNT = 25? Yes Data = 01h? Increment PLSCNT Yes No Yes No Read from sector address with A6 = 1, A1 = 1, A0 = 0 Set up next sector address Device failed Protect another sector? No Remove VID from RESET# PLSCNT = 1000? Yes Data = 00h? Yes Device failed Write reset command Last sector verified? Yes No Sector Protect Algorithm Sector Protect complete Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Figure 2. In-System Sector Protect/ Unprotect Algorithms AM29LV033C 15 Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 9 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must pro- vide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5-8. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 5-8. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/products/nvd/overview/cfi.html. Alternatively, contact an AMD representative for copies of these documents. Table 5. Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 51h 52h 59h 02h 00h 40h 00h 00h 00h 00h 00h CFI Query Identification String Description Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) 16 AM29LV033C Table 6. Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 27h 36h 00h 00h 04h 00h 0Ah 00h 05h 00h 04h 00h System Interface String Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) Table 7. Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 16h 00h 00h 00h 00h 01h 3Fh 00h 00h 01h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Device Geometry Definition Description Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information AM29LV033C 17 Table 8. Addresses 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch Data 50h 52h 49h 31h 30h 01h 02h 01h 04h 04h 20h 00h 00h Primary Vendor-Specific Extended Query Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0 = Required, 1 = Not Required Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect: 04 = Supported Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800A mode Simultaneous Operation: 20 = Not Supported Burst Mode Type: 00 = Not Supported, 01 = Supported Page Mode Type: 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 18 AM29LV033C COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 9 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 9 shows the address and data requirements. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Figure 13 shows the timing diagram. Byte Program Command Sequence The device programs one byte of data for each program operation. The command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 9 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command se- Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. AM29LV033C 19 quence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set DQ5 to "1," or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1". Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 9 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don't cares for both cycles. The device then returns to reading array data. Accelerated Program Operations The device offers accelerated program operations through the ACC pin. When the system asserts VHH on the ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence, eliminating two cycles from the command sequence. In addition, the device uses the higher voltage on the ACC pin to accelerate the operation. Note that the ACC pin must not be at VHH during read or erase operations, or device damage may result. If ACC is to be permanently set, it is recommended that it be tied to VCC to minimize current consumption. Figure 3 illustrates the algorithm for the program operation. See the Erase/Program Operations table in "AC Characteristics" for parameters, and to Figure 15 for timing diagrams. Embedded Program algorithm in progress START Write Program Command Sequence Data Poll from System Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed Note: See Table 9 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 9 shows the address and data requirements for the chip erase command sequence. Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset dur ing the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the de- 20 AM29LV033C vice has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to Figure 17 for timing diagrams. mands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to "Write Operation Status" for information on these status bits.) Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to Figure 17 for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 9 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the "DQ3: Sector Erase Timer" section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com- Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the time-out period 50 s during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are "don't-cares" when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard pro- AM29LV033C 21 gram operation. See "Write Operation Status" for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Notes: 1. See Table 9 for erase command sequence. 2. See "DQ3: Sector Erase Timer" for more information. Figure 4. Erase Operation 22 AM29LV033C Table 9. Command Sequence (Note 1) Read (Note 5) Reset (Note 6) Manufacturer ID (Note 8) Autoselect (Note 7) Device ID (Note 8) Sector Protect Verify (Note 9) Cycles First AM29LV033C Command Definitions Bus Cycles (Notes 2-4) Second Third Addr Data Fourth Addr Fifth Sixth Addr Data Addr Data Addr Data RA XXX XXX XXX XXX RD F0 AA AA AA AA AA A0 90 AA AA B0 30 98 XXX XXX XXX XXX XXX XXX PA XXX XXX XXX 55 55 55 PD 00 55 55 55 55 Data Addr Data 1 1 4 4 4 4 3 2 2 6 6 1 1 1 0XXXXX 0XXXXX 0XXXXX or 2XXXXX XXX XXX 90 90 90 A0 20 0XXX00 0XXX01 SA X02 PA 01 A3 00 01 PD XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX Byte Program Unlock Bypass Unlock Bypass Program (Note 10) Unlock Bypass Reset (Note 11) Chip Erase Sector Erase Erase Suspend (Note 12) Erase Resume (Note 13) CFI Query (Note 14) XXX XXX 80 80 XXX XXX AA AA XXX XXX 55 55 XXX SA 10 30 Legend: X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE# or CE# pulse. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# pulse. SA = Address of the sector to be erased or verified. Address bits A21-A16 uniquely select any sector. Notes: 1. See Table 1 for descriptions of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all bus cycles are write operations. 4. Address bits are don't care for unlock and command cycles, except when PA or SA is required. 5. No unlock or command cycles required when device is in read mode. 6. The Reset command is required to return to the read mode when the device is in the autoselect mode or if DQ5 goes high. 7. The fourth cycle of the autoselect command sequence is a read cycle. 8. In the third and fourth cycles of the command sequence, set A21 to 0. 9. In the third cycle of the command sequence, address bit A21 must be set to 0 if verifying sectors 0-31, or to 1 if verifying sectors 32-64. The data in the fourth cycle is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 10. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the Unlock Bypass mode. 12. The system may read and program functions in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 13. The Erase Resume command is valid only during the Erase Suspend mode. 14. Command is valid when device is ready to read array data or when device is in autoselect mode. AM29LV033C 23 WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 10 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. Table 10 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. START DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7-DQ0 on the following read cycles. This is bec a u s e D Q 7 m ay ch a n g e a s yn c h ro n o u s l y w i t h DQ0-DQ6 while Output Enable (OE#) is asserted low. F i g u r e 1 8 , D a t a # Po l l i n g T i m i n g s ( D u r i n g Embedded Algorithms), in the "AC Characteristics" section illustrates this. Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm 24 AM29LV033C RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 10 shows the outputs for RY/BY#. Figures 14, 15 and 17 shows RY/BY# for reset, program, and erase operations, respectively. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 10 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section "Reading Toggle Bits DQ6/DQ2" explains the algorithm. Figure 19 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. DQ2: Toggle Bit II The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 10 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section "Reading Toggle Bits DQ6/DQ2" explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 19 shows the toggle bit timing diagram. Figure 20 shows the differences between DQ2 and DQ6 in graphical form. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle (The system may use either OE# or CE# to control the read cycles). When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer 25 AM29LV033C toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6). Table 10 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm. Figure 19 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. START Read DQ7-DQ0 (Note 1) Read DQ7-DQ0 Toggle Bit = Toggle? Yes No No DQ5 = 1? DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data. Yes (Notes 1, 2) Read DQ7-DQ0 Twice Toggle Bit = Toggle? No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from "0" to "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to "1". See text. Figure 6. Toggle Bit Algorithm DQ3 is "1", the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0", the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 10 shows the outputs for DQ3. 26 AM29LV033C Table 10. Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program Write Operation Status DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0 DQ7 (Note 2) DQ7# 0 1 Data DQ7# Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See "DQ5: Exceeded Timing Limits" for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. AM29LV033C 27 ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . .-0.5 V to +4.0 V A9, OE#, and RESET# (Note 2) . . . . . . . . . . . .-0.5 V to +12.5 V All other pins (Note 1) . . . . . . .-0.5 V to VCC+0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA). . . . . . . . . . . .0C to +70C Industrial (I) Devices Ambient Temperature (TA). . . . . . . . . .-40C to +85C Extended (E) Devices Ambient Temperature (TA). . . . . . . . .-55C to +125C VCC Supply Voltages VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. 20 ns +0.8 V VSS-0.5 V VSS-2.0 V 20 ns 20 ns VCC+2.0 V VCC+0.5 V 2.0 V 20 ns 20 ns 20 ns Figure 7. Maximum Negative Overshoot Waveform Figure 8. Maximum Positive Overshoot Waveform 28 AM29LV033C DC CHARACTERISTICS CMOS Compatible Parameter ILI ILIT ILO Description Input Load Current (Note 1) A9 Input Load Current Output Leakage Current VCC Active Read Current (Notes 2, 3) VCC Active Write Current (Notes 2, 4, 6) VCC Standby Current (Note 2) VCC Reset Current (Note 2) Automatic Sleep Mode (Notes 2, 5) ACC Accelerated Program Current, Word or Byte Input Low Voltage Input High Voltage Voltage for ACC Sector Protect/Unprotect and Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 6) VCC = 3.0 V 10% Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC max 5 MHz CE# = VIL, OE# = VIH 1 MHz 10 2 15 0.2 0.2 Min Typ Max 1.0 35 1.0 16 mA 4 30 5 5 mA A A Unit A A A ICC1 ICC2 ICC3 ICC4 CE# = VIL, OE# = VIH CE#, RESET#, ACC = VCC0.3 V RESET# = VSS 0.3 V, ACC = VCC 0.3 V VIH = VCC 0.3 V; VIL = VSS 0.3 V, ACC = VCC 0.3 V ACC pin VCC pin -0.5 0.7 x VCC 8.5 ICC5 0.2 5 A 5 15 10 30 0.8 VCC + 0.3 9.5 mA mA V V V IACC CE# = VIL, OE# = VIH VIL VIH VHH VID VOL VOH1 VOH2 VLKO VCC = 3.3 V IOL = 4.0 mA, VCC = VCC min IOH = -2.0 mA, VCC = VCC min IOH = -100 A, VCC = VCC min 11.5 12.5 0.45 V V V 0.85 VCC VCC-0.4 2.3 2.5 V Notes: 1. On the ACC pin only, the maximum input load current when ACC = VIL is 5.0 A. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. The ICC current listed is typically is less than 2 mA/MHz, with OE# at VIH. Typical specifications are for VCC = 3.0 V. 4. ICC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 6. Not 100% tested. AM29LV033C 29 DC CHARACTERISTICS (Continued) Zero Power Flash 25 Supply Current in mA 20 15 10 5 0 0 500 1000 1500 2000 Time in ns Note: Addresses are switching at 1 MHz 2500 3000 3500 4000 Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 12 3.6 V 10 2.7 V 8 Supply Current in mA 6 4 2 0 1 Note: T = 25 C 2 3 Frequency in MHz Figure 10. Typical ICC1 vs. Frequency 4 5 30 AM29LV033C TEST CONDITIONS Table 11. 3.3 V Test Condition Device Under Test CL 6.2 k Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels 5 0.0-3.0 1.5 1.5 ns V V V 2.7 k Output Load Output Load Capacitance, CL (including jig capacitance) 30 -70 -90, -120 1 TTL gate 100 pF Unit Test Specifications Note: Diodes are IN3064 or equivalent Figure 11. Test Setup Output timing measurement reference levels KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS 3.0 V 0.0 V Input 1.5 V Measurement Level 1.5 V Output Figure 12. Input Waveforms and Measurement Levels AM29LV033C 31 AC CHARACTERISTICS Read Operations Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ Std tRC tACC tCE tOE tDF tDF Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Read tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling CE# = VIL OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Min Min Min Speed Option -70 70 70 70 30 25 25 -90 90 90 90 40 30 30 0 10 0 -120 120 120 120 50 30 30 Unit ns ns ns ns ns ns ns ns ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Notes: 1. Not 100% tested. 2. See Figure 11 and Table 11 for test specifications. tRC Addresses CE# tOE tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tDF Addresses Stable tACC OE# 0V Figure 13. Read Operations Timings 32 AM29LV033C AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std tREADY tREADY tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) RESET# Pulse Width RESET# High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Test Setup Max Max Min Min Min Min All Speed Options 20 500 500 50 20 0 Unit s ns ns ns s ns Note: Not 100% tested. RY/BY# CE#, OE# tRH RESET# tRP tReady Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms tReady RY/BY# tRB CE#, OE# RESET# tRP Figure 14. RESET# Timings AM29LV033C 33 AC CHARACTERISTICS Erase/Program Operations Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX Std tWC tAS tAH tDS tDH tOES tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH1 tWHWH2 tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH1 tWHWH2 tVCS tRB tBUSY Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time (Note 1) Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Programming Operation (Note 2) Accelerated Programming Operation (Note 2) Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Min 30 45 35 -70 70 Speed Option -90 90 0 45 45 0 0 0 0 0 45 30 9 7 0.7 50 0 90 50 50 50 -120 120 Unit ns ns ns ns ns ns ns ns ns ns ns s s sec s ns ns Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. 34 AM29LV033C AC CHARACTERISTICS Program Command Sequence (last two cycles) tAS tWC Addresses XXXh PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# tVCS VCC Status DOUT tRB tWPH tWHWH1 Read Status Data (last two cycles) PA PA tCH A0h Note: PA = program address, PD = program data, DOUT is the true data at the program address. Figure 15. Program Operation Timings VHH ACC VIL or VIH tVHH tVHH VIL or VIH Figure 16. Accelerated Program Timing Diagram AM29LV033C 35 AC CHARACTERISTICS Erase Command Sequence (last two cycles) tAS tWC Addresses XXXh SA XXXh for chip erase Read Status Data VA VA tAH CE# OE# tWP WE# tCS tDS tCH tWPH tWHWH2 tDH Data 55h 30h 10 for Chip Erase In Progress Complete tBUSY RY/BY# tVCS VCC tRB Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status"). Figure 17. Chip/Sector Erase Operation Timings 36 AM29LV033C AC CHARACTERISTICS tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7 High Z VA VA tOE tDF Complement Complement True Valid Data High Z DQ0-DQ6 tBUSY RY/BY# Status Data Status Data True Valid Data Note: VA = Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 18. Data# Polling Timings (During Embedded Algorithms) tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ6/DQ2 tBUSY RY/BY# Note: VA = Valid address; not required for DQ6. Figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. High Z VA VA VA tOE tDF Valid Status (first read) Valid Status (second read) Valid Status (stops toggling) Valid Data Figure 19. Toggle Bit Timings (During Embedded Algorithms) Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note: The system can use OE# or CE# to toggle DQ2/DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 20. DQ2 vs. DQ6 AM29LV033C 37 AC CHARACTERISTICS Temporary Sector/Sector Block Unprotect Parameter JEDEC Std tVIDR tRSP Description VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector/Sector Block Unprotect Min Min All Speed Options 500 4 Unit ns s Note: Not 100% tested. 12 V RESET# 0 or 3 V tVIDR Program or Erase Command Sequence CE# tVIDR WE# tRSP RY/BY# Figure 21. Temporary Sector/Sector Block Unprotect Timing Diagram 38 AM29LV033C VID VIH RESET# SA, A6, A1, A0 Valid* Sector/Sector Block Protect or Unprotect Valid* Verify 40h Sector/Sector Block Protect: 150 s, Sector/Sector Block Unprotect: 15 ms Valid* Data 60h 60h Status 1 s CE# WE# OE# Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 22. Sector Protect/Unprotect Timing Diagram AM29LV033C 39 AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter JEDEC tAVAV tAVEL tELAX tDVEH tEHDX Std tWC tAS tAH tDS tDH tOES tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Output Enable Setup Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) Sector Erase Operation (Note 2) Min Min Min Min Min Min Min Min Min Min Min Typ Typ 30 45 35 -70 70 Speed Option -90 90 0 45 45 0 0 0 0 0 45 30 9 0.7 50 50 50 -120 120 Unit ns ns ns ns ns ns ns ns ns ns ns s sec Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information. 40 AM29LV033C AC CHARACTERISTICS XXX for program XXX for erase PA for program SA for sector erase XXX for chip erase Data# Polling PA Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tAS tAH tWHWH1 or 2 tBUSY DQ7# DOUT RESET# RY/BY# Notes: 1. PA = Program Address, PD = Program Data, DOUT = Data Out, DQ7# = complement of data written to device. 2. Figure indicates the last two bus cycles of the command sequence. Figure 23. Alternate CE# Controlled Write Operation Timings AM29LV033C 41 ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Programming Time Accelerated Byte Program Time Chip Programming Time (Note 3) Typ (Note 1) 0.7 45 9 7 36 300 210 108 Max (Note 2) 15 Unit s s s s s Excludes system level overhead (Note 5) Comments Excludes 00h programming prior to erasure (Note 4) Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four- or two-bus-cycle sequence for the program command. See Table 9 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min -1.0 V -1.0 V -100 mA Max 12.5 V VCC + 1.0 V +100 mA Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP PIN CAPACITANCE Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz. DATA RETENTION Parameter Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years 42 AM29LV033C PHYSICAL DIMENSIONS* TS 040--40-Pin Standard TSOP Dwg rev AA; 10/99 * For reference only. BSC is an ANSI standard for Basic Space Centering. AM29LV033C 43 PHYSICAL DIMENSIONS TSR040--40-Pin Reverse TSOP Dwg rev AA; 10/99 * For reference only. BSC is an ANSI standard for Basic Space Centering. AM29LV033C 44 PHYSICAL DIMENSIONS FBD063--63-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm Dwg rev AF; 10/99 45 AM29LV033C REVISION SUMMARY Revision A+1 (January 1999) Device Bus Operations Sector/Sector Block Addresses for Protection/Unprotection Table: Corrected the address bits and values in the middle column of the table. Revision A+7 (August 2, 1999) Block Diagram Added ACC signal to drawing. Accelerated Program Operations Clarified how to permanently set ACC. Accelerated Program Timing Diagram Deleted WP# designation from ACC signal. Autoselect Codes (High Voltage Method Table: Changed the device ID to A3h. Revision A+2 (January 1999) Command Definitions Revision A+8 (August 18, 1999) Ordering Information, Physical Dimensions Corrected FBGA package dimensions to 8 x 14 mm. Command Definition Table: Changed the device ID to A3h. Revision A+3 (March 17, 1999) Connection Diagrams Modified FBGA drawing to show how outrigger balls are shorted. Revision A+9 (August 31, 1999) Ordering Information Speed Option: Changed 70R to 70. Revision A+4 (May 17, 1999) Global Deleted references to WP#. The device does not offer this function. Table 4. Sector Block Addresses for Protection/Unprotection Deleted "Top Boot Sector/" from table title. Revision B (January 3, 2000) AC Characteristics--Figure 15. Program Operations Timing and Figure 17. Chip/Sector Erase Operations Deleted tGHWL and changed OE# waveform to start at high. Physical Dimensions Replaced figures with more detailed illustrations. Revision A+5 (June 7, 1999) Global The 70 ns speed option now operates over the full 2.7-3.6 V VCC range. Common Flash Memory Interface Corrected data for the following addresses: 27h, 2Dh, 37h, 48h, and 49h. Modified the description for 48h and 49h. Revision B+1 (February 21, 2000) Global Changed data sheet status to "Preliminary" from "Advance Information. Added dash to speed options. Ordering Information Added dash to OPN. Revision A+6 (June 25, 1999) Command Definitions Table Indicated that address bit A21 must be specified in the third cycle when entering the autoselect mode. Revision B+2 (November 7, 2000) Global Added Table of Contents. Deleted burn-in option. Deleted Preliminary status from data sheet. AM29LV033C 46 Trademarks Copyright (c) 2000 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 47 AM29LV033C |
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